A Novel EDA flow for SoC Designs based on Specification Capture, Block-clustering and Bus-partitioning

The RTL-to-GDSII tool suites are already being used in order to carry out the logical or register transfer level (RTL) design and synthesis, in tandem with floor planning, placement and routing, to expedite the process of ASIC design production. This paper proposes a novel EDA flow for SoC designs based on the block clustering and bus-partitioning techniques which starts at the design specification capture level finally giving the required SoC. Conventionally an UML (Unified Modelling Language) can be used to model reusable components at higher levels of abstraction and System level design languages (SLDL) such as SpecC, SystemC etc., provide a platform for generating “executable specification” that describe the functionality of the system along with performance, cost and other constraints, without including prematurely developed implementation details. Since the UML is not executable and the functionality depicted in the model cannot be verified for accuracy, the authors present a system modeling aspect, which binds these two technologies and provides a platform for interoperability between UML and SLDLs. The correctness of the specification is checked at this stage. Further, the methodology explained in this paper clusters both the macro and micro blocks, based on the communication traffic between each of the blocks, and performs intermediate floor planning to facilitate designers to estimate the area of the design, to reduce the avoidable increase in power consumption of the chip prior to placement and routing by assuring the placement of the clustered macro-blocks near the power grids and to have a timing efficient system.